1. Field of the Invention
The present invention relates generally to semiconductor wafers and wafer fabrication, and more particularly, to a semiconductor wafer wherein step coverage along the scribe lines thereof is improved over that of the prior art.
2. Description of the Prior Art
In a semiconductor wafer fabrication process, a semiconductor wafer is partitioned into a multiplicity n of chip or die areas defined by a grid-like array of scribe lines which are inscribed into the surface of the wafer. Then, an identically patterned, multilayer structure is simultaneously fabricated in each of the chip areas, with the exception of a few test chip areas. Generally, each of these patterned multilayer structures constitutes a single, discrete semiconductor device or integrated circuit (I.C.). Ultimately, the wafer is sliced, e.g., by means of a diamond-tipped cutting tool, along the scribe lines, into a multiplicity n of individual I.C. chips or die.
In the fabrication of I.C.s having high levels of integration (e.g., VLSI), the number of patterned layers required to make the I.C.s is large, which occasions certain problems which complexify the wafer fabrication process and degrade wafer yield. More particularly, the peripheral edge portion of the patterned multilayer structure of each individual I.C. fabricated on the wafer, extends into the scribe line region between adjacent ones of the I.C.s. As part of the fabrication process, a sequence of photolithographic steps are performed in order to create the desired pattern in each of the individual layers of the eventual multilayer structure of each I.C. It is critical to the efficacy of this process that the photoresist film deposited on each layer to be patterned, be deposited evenly and uniformly, and at the proper thickness. However, when the number of individual layers to be patterned becomes too large, the height of the vertical steps formed at the peripheral edge of the patterned multilayer structure of each I.C. becomes so great as to cause thinning or attenuation of the photoresist film deposited thereover, a condition which is generally referred to an inadequate step coverage.
Such inadequate step coverage results in degradation of the electrical characteristics, performance, and reliability of the individual I.C.s fabricated in the wafer. Further, such inadequate step coverage causes an increase in the number of defective die per wafer, thereby lowering wafer yield. This problem of inadequate step coverage becomes more acute as the level of integration density of the I.C.s becomes greater, thereby resulting in increased height of the vertical steps formed at the peripheral edge of the patterned multilayer structure of each I.C., which, in turn, aggravates the problem of inadequate step coverage.